UART

Universal Asynchronous Receiver and Transmitter

Transmit: Uses Shift Register to compile Parallel Data -> Serial

Receiver: Uses Shift Register to compile Serial data -> Parallel

Data Transmission

One byte at a time

1. Idle Transmission -> All bits will be 1
2. Start bit -> 0
3. Followed by 8 data bits
4. Stop bit -> 1

Shift Register

A series of flip flops that can turn serial data <--> parallel

Ingests these values at a specific Baud Rate

Baud Rate

Bits per second

Example

9600 Baud = 9600 bits / second (Binary Signaling)

RC4 Algorithm

• Stream cipher
  • One bit at a time
• Key input:
  • random bit gen -> 8 bit number
  • Key generation algorithm -> Key Scheduling Algorithm

Key Generation Algorithm

User selects key(1-256bytes, typically 5-16 bytes), which generates 256byte state vector S.

Initialize array S[char] of size 256 bytes

S = [x for x in range(0,256)]
S = [0,1,2,3,...,255]

Key-Scheduling Algorithm

A simple loop that rearranges array S by swapping its elements at certain points -> KSA Scrambling

key_scheduling():
    j = 0
    for i in range(0, keyLength):
        i %= keyLength 
        j = j ( j + S[i] + key[i] ) % keyLength
        S[i], S[j] = S[j], S[i] # Bit swapping

Pseudo-random Generator

(The actual Keystream to be XOR with Plaintext Stream)

j = 0

for i in range(1, len(plaintext) + 1):
    i %= keyLength
    j = (j+S[i]) % keyLength
    
    S[i], S[j] = S[j], S[i] # More swapping
    t = ( S[i] + S[j] ) + keyLength
    
    push S[t] # <- Push key stream bit-by-bit

Example

Encryption

Plaintext = 10011000 Key = 01010000 $$ Plaintext \oplus Key = Ciphertext $$ $$ 10011000 \oplus 01010000 = 11001000
$$ Cipher text = 11001000

Decryption

Cipher text = 11001000 Key = 01010000 $$ Ciphertext \oplus Key = Plaintext $$ $$ 11001000 \oplus 01010000 = 10011000
$$

Plaintext = 10011000